1. Related Applications
This application claims priority from International Application No. PCT/JP03/002511, filed Mar. 4, 2003, which claims priority of Japanese Patent Application No. 2002-82451, filed on Mar. 25, 2002.
2. Field of the Invention
The present invention relates to a thin film transistor, a circuit apparatus including the thin film transistor, a liquid crystal display including the thin film transistor, and a liquid crystal display including the circuit apparatus.
3. Description of Prior Art
A thin film transistor (referred to as “TFT” hereinafter) is used as, for example, a switching device for a pixel of a liquid crystal display, a component device for a peripheral circuit apparatus and so forth.
The TFT includes an active layer made of a one conductive type formed semiconductor. This active layer includes a source region as well as a drain region, both of which are formed by doping a part of the semiconductor of the active layer with high concentrated impurities. A gate electrode is formed above or below a channel region with a gate insulating film interposed therebetween, the channel region being located between these source and drain regions.
As the active layer, for example, an n-channel type polycrystalline silicon film (Poly-Si film) is used.
So far, when forming a plurality of TFTs including an active layer having a source region and a drain region, on a sheet of substrate, there has been caused such a problem that the electrical properties of each TFT becomes uneven due to the difference in the grain size and the plane direction in each grain in the active layer. Accordingly, as a means of solving this problem, it is required to enlarge the grain size.
With regard to a method of enlarging the grain size in a semiconductor layer directly or indirectly formed on a sheet of substrate, some reports have been already made(e.g., see to Non-Patent Document 1). However, it is not possible to control the crystal orientation in the in-plane direction of the semiconductor layer by means of these techniques as disclosed.
There are some reports reporting that unevenness in the electrical property of a circuit apparatus including TFTs depends on the aforesaid crystal orientation (e.g., see Non-Patent Document 2 as shown later). This will be described referring to FIG. 15.
FIG. 15 is a schematic plan view for indicating an example of grains and grain boundaries in an active layer made of semiconductor in a prior art TFT.
In FIG. 15, there is shown a part of a semiconductor film in which, 100 denotes a grain of semiconductor, 101 a grain boundary, 102 an active layer, and 103 the flow direction of electric current flowing in the active layer 102, respectively. The active layer 102 is a layer made of one conductive type formed semiconductor.
The electrical property of the TFT varies depending on the number of the grains 100 or grain boundaries 101 in the active layer 102. When the electric current flows in the direction as shown by an arrow 103 passing through the active layer 102 including a lot of grain boundaries 101, the number of times the electric current goes across the grain boundaries 101 varies from TFT to TFT. Accordingly, there is caused such a problem that the electrical property of each TFT formed on a sheet of substrate can not become uniform.
In case of forming a TFT including such an active layer that is formed by using a part of the aforesaid Poly-Si film as the active layer 102, as it is not possible to control the crystal orientation of each silicon grain 100 in the active layer, it is so difficult to reduce the unevenness in the electrical property due to the different plane direction. Especially, when the channel length is small, as the occupation rate that one grain 100 occupies the active layer 102 becomes large, there is caused such a problem that it is not possible to lessen the unevenness in the electrical property of the prior art TFT.
Furthermore, there are some papers reporting that the unevenness in the electrical property of each TFT like this is caused by that the grain boundary 101 forms a high potential barrier height in the active layer 102 made of polycrystalline silicon, thereby lowering the field-effect mobility of the TFT (e.g., see Non-Patent Document 3).
The grain boundary 101 standing in the direction crossing the moving direction of electron or hole as a carrier of electric charge and the grain boundary 101 standing in the almost same direction as the moving direction give different influence to the electrical property of the TFT, respectively.
As a result, even if the TFT is formed on an identical substrate, there is caused such a problem that the electrical property of the TFT becomes different.
Non-Patent Document 1: Masakiyo Matsumura “Preparation of Ultra-Large Grain Silicon Thin-Films by Excimer-Laser” (Journal of The Surface Science Society of Japan, “Surface Science,” Vol. 21, No. 5, pp. 278–287 (pp. 34–43), 2000, The Surface Science Society of Japan).
Non-Patent Document 2: Bernd Goebel et al., Electron Devices, IEEE Transactions, Vol. 48, No. 5, pp.897–905, May 2001.
Non-Patent Document 3: Levinson et al., Journal of Applied Physics, Vol. 53, No. 2, pp. 1193–1202, February 1982.
Non-Patent Document 4: Research And Development Association For Future Electron Devices Incorporated Foundation, “Research And Development Project on Three-Dimension Integrated Circuit,” pp. 87–104, Oct. 23, 1991.